1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a data output buffer of a semiconductor memory device using a clock of a constant period applied from an external source.
2. Background of the Related Art
A dynamic RAM (random access memory), which is representative of a read/write memory in a semiconductor memory device, performs data read and write operations subsequent to receipt of a row address strobe signal from the exterior of the memory chip.
A data output operation of a conventional dynamic RAM will now be described with reference to FIGS. 1A and 1B. A row address RA is entered after an inverse row address strobe signal RAS is enabled to logic "low" state. After the inverse row address strobe signal RAS enters to an active cycle, inverse column address strobe signal CAS is enabled to logic "low" state, a column address CA is entered. Data stored memory cell designated by a corresponding address is sensed through a sense amplifier and then generated through a data output buffer. In this data output buffer, a data path is cut off or connected by an output enable signal OE. As is well known, the output enable signal OE is generated using a control clock supplied by a central processing unit memory external to the memory chip and a signal relating to a data sensing state within the memory chip.
In a typical semiconductor memory device such as a dynamic RAM, a time "t" to generate output data after the inverse row address strobe signal RAS is enabled is nearly constant. Similarly, a time t to generate the output data after the inverse column address strobe signal CAS is enabled is nearly constant. This is because after the row address RA and the column address CA are entered, processes for sensing the data from the designated memory cell and generating the output data are executed sequentially in repetitive manner each time.
As part of this repetitive process, the output enable signal OE enables the data output buffer time t after the inverse row address stroke RAS in order to generate correct output data through the data output buffer. In a synchronous dynamic RAM, since the output enable signal OE is enabled a time t after the inverse column address strobe signal CAS is enabled, incorrect output data due to enabling the data output buffer at a undesired time does not occur. Thus, in a conventional semiconductor memory device which does not use a system clock, a determination of the timing output enable signal OE should consider the time needed to generate developed data through a sense amplifier to an input side of the data output buffer in order for the data output buffer to operate at a desired time on the data being input.
As is well known, the operating frequency of semiconductor memory devices is slower than the operating frequency of a typical central processing unit. In a high-performance dynamic RAM that achieves high speed operation (or the reduction of a data access time), it is desirable to control read and write operations by synchronizing with a clock supplied from the central processing unit. In these semiconductor memory devices (hereinafter, referred to as synchronous memory devices), since the timing of the data output is synchronized with multiple pulse periods of the system clock, the data output buffer should be enabled in consideration of the time t. For example, when a system clock of 66 MHz among the system clocks ranging from 33 MHz to 100 MHz is supplied from the central processing unit if it is constructed such that the data output buffer is enabled at a rising edge of a second pulse of the system clock which occurs after the inverse column address strobe signal CAS is enabled (i.e. after the falling edge), the data output buffer is enabled after 15 ns (nano seconds) corresponding to a first period.
On the other hand, when the system clock of 100 MHz is supplied, if it is constructed such that the data output buffer is enabled at the rising edge of at least a third pulse of the system clock which occurs after the inverse column address strobe signal CAS is enabled, the data output buffer is enabled after 20 ns corresponding to a second period. If the time needed to generate data to the input side of the data output buffer after the inverse column address strobe signal CAS is enabled is 25 ns, if the system clock of 66 MHz is supplied, the data output buffer is enabled before the data is generated to the input side thereof, thereby generating erroneous output data.